The present invention is concerned generally with logic analysis instruments capable of selecting data or being triggered within a predetermined range of addresses, and more particularly to a programmable range recognizer for a logic analyzer.
A logic analyzer is an electronic instrument which captures and displays the flow of events in the form of logic states of parallel-bit data occurring in a digital system. The data which are acquired for display are first stored in a memory device, and because of limited acquisition memory space, the starting point for data collection must first be defined and the information to be stored first must be selected in order to store only that to be displayed. Defining the starting point and selecting the data to be captured are known in the logic analyzer art as triggering and qualification, respectively. Typically, so-called word recognizers, which are set to recognize a specific pattern of parallel bits, or digital words, are utilized for both triggering and data qualification. In more sophisticated logic analyzers, particular sequences of events rather than a single digital word may be specified for triggering or data qualification.
In using the logic analyzer to analyze software and hardware situations associated with microprocessors, it is often desirable to be able to trigger on a range of words, such as, for example, a range of addresses on the address bus, or to qualify such data for acquisition. Furthermore, it would be desirable that such a range recognizer be programmable to provide a flexible range recognition system for triggering or data qualification. However, for wide address buses, for example, for a common bus width of 24 bits, implementation of address range recognition has been considered impractical and rather cumbersome because of the huge number of address possibilities.